1. Field of the Invention
This invention relates to a semiconductor integrated circuit with an input buffer circuit having a power consumption-saving function.
2. Prior Art
FIG. 1 shows the arrangement of an input buffer circuit provided with a pull-up function, which is employed in a conventional MOS integrated circuit. The input buffer circuit 3 is constituted by CMOS inverters 3a and 3b arranged in two stages, with an input terminal thereof connected to an external signal input pad 1. The input terminal of the input buffer circuit 3 is also connected to an input protection circuit 2 formed by diodes D1 and D2, while a p-channel MOS transistor hereinafter referred to as "the PMOS transistors") QP0 as a pull-up resistor is connected between the input terminal and a power supply V.sub.DD. The PMOS transistor QP0 has its gate grounded.
The PMOS transistor QP0 as the pull-up resistor is a type having a high ON-state resistance. This makes it possible to transmit changes in signal level at the external signal input pad 1 to the input buffer circuit 3, and at the same time hold the input terminal of the input buffer circuit 3 at the voltage of the power supply V.sub.DD without making the input terminal floating even when the external signal input pad 1 is made open.
The conventional input buffer circuit with a pull-up function shown in FIG. 1 cannot reduce the power consumption to a sufficiently low level for the following reasons, particularly when it is used in an integrated circuit with a power-down mode in which an internal circuit thereof is set to a power-saving state when the integrated circuit is on standby: First, when the external signal input pad 1 is grounded, for example, with the internal circuit in the power-down mode, a steady-state current flows from the power supply V.sub.DD through the PMOS transistor QP0 as the pull-up resistor to the external signal input pad 1 which is grounded. Secondly, if the internal circuit is set to the power-down mode when the signal level at the external signal input pad 1 undergoes changes between an "L" level and an "H" level, the inverters 3a and 3b of the input buffer circuit 3 repeatedly make a state transition, which causes a current to flow through the input buffer circuit 3 in each transitional state.